(1) Field of the Invention
This invention relates generally to vertically stacked wafer level packaging of silicon device wafers . . . More particularly it relates to the process used for separating two or more bonded wafers for various applications like fabrication of through-hole interconnected substrates, 3D stacked wafer level packaging, transfer of films or device structures by transfer-bonding, etc.
(2) Description of the Prior Art
Modular systems packaging applications are increasingly in demand as more and more devices with different applications are integrated together. High density and high speed transmission are additional requirements for future products. Multi chip module (MCM) is one of the methods in which different devices can be integrated together in a 2D approach. However, the final assembly is larger in size and miniaturization is limited. Since the size of the product is shrinking and, at the same time, more functions are integrated, the MCM approach is not a viable solution for the next generation microsystem packaging. Product shrinking has become like a natural phenomenon and the challenge ahead is how to make the package size smaller, but with higher performance while meeting reliability requirements. Integrating devices in a vertical fashion can reduce the real estate of the total package. 3D integration can be achieved by stacking the packages or by stacking the dies or by stacking the wafers. An easy way of realizing this approach is by stacking the chips one over the other and wire bonding the chips. A conventional method of interconnecting the stacked chips is by side wall contacts with metallization. In the above approach, the assembly is done at chip level and assembly cost is high due to chip processing.
Vertical integration of wafers is based on thinning, bonding, and interconnecting the wafer by through-hole filled vias. Through-wafer vias are typically intended for providing interconnects between both sides of wafers with microdevices and are fabricated using wafer level packaging (WLP). Current packaging trends show that vertical interconnects are favored because of space efficiency, design simplicity, heterogeneous integration, and low parasitic capacitance and impedance.
In the prior art, the article entitled “Through-wafer copper electroplating for three-dimensional ICs” by N. T. Nguyen et al, Institute of Physics Publishing, Journal of Micromechanics and Microengineering, c. 2002, pp. 395–399, proposes a method using wafer to wafer bonding with a photoresist layer as a bonding material to form through-wafer vias in a wafer. The wafer with through-wafer vias is first bonded to another wafer with a seed metal layer using the photoresist layer sandwiched between the seed metal layer and the wafer with through-wafer vias for the bonding. The photoresist layer exposed by the through-wafer vias is then subjected to exposure and development through the through-wafer vias to form seed areas. Once the seed areas are formed, electroplating is performed to fill the through-wafer vias using these seed areas. After the via filling, the sacrificial wafer has to be removed to separate the via-filled wafer for subsequent process integration. In this article, no method is mentioned for separating the wafer from the sacrificial wafer. Photoresist bonding cannot be removed by chemical processing methods since the vias are attached to the sacrificial wafer. One possible method could be by a conventional method such as a back grinding method. Since photoresist bonding is not uniform and the strength is poor, the wafer can break during the thinning process. In this case, the sacrificial wafer cannot be removed completely.
Another prior art article entitled “A Novel Electrically Conductive Wafer Through Hole Filled Vias Interconnect For 3D MEMS Packaging” by C. S. Premachandran et al, 2003 Electronic Componenets and Technology Conference, c. 2003 IEEE, pp. 627–630, gives details on the through-hole via filling with a sacrificial wafer attached to the via wafer. In this method, the sacrificial wafer is bonded to the via wafer using metal bonding by thermo-compression. Metal bonding is stronger than the photoresist bonding and will not be affected by the electroplating process. In this case the bonding integrity is good compared to resist bonding. The sacrificial wafer is removed by a wafer grinding method. In this method, wafer bonding equipment is required to bond the sacrificial wafer to the through-hole wafer. Wafer bonding equipment is expensive and carries an additional cost to the final product. Also, thermo-compression bonding happens at a higher temperature (above 350° C.) causing additional thermal stress to be applied to the wafer. Another process involved in this method is the back grinding process. It is a destructive process of physically removing the material by lapping/polishing methods. When removing the material by a back grinding method, mechanical stress is generated and transmitted to the through-hole via wafer. This poses a serious reliability issue for subsequent processes for the through-hole via wafer. A backgrinding process can also damage the sacrificial wafer if the bonding strength between the two wafers is not sufficient. This creates an earlier break or cracks on the sacrificial wafer and, subsequently, the machine stops and the further grinding process is affected. In this method, two additional processes are required increasing the cost of the final product.
Transfer bonding is discussed in the article “Wafer-level membrane transfer bonding of polycrystalline silicon bolometers for use in infrared focal plane arrays” by F. Niklaus et al, Journal of Micromechanics and Microengineering, 2001, p. 509–513.